Gate charge behaviors in N-channel power VDMOSFETs during

Publication

Gate charge behaviors in N-channel power VDMOSFETs during HEF and PBT stresses

Microelectronics Reliability 47 (2007) 1406–1410

M. Alwan a,*, B. Beydoun b, K. Ketata c, M. Zoaeter b

a LEMI, Rouen University, 76821 Mont Saint Aignan, France

b LPM, Lebanese University, P.O. Box 11-4661, Beirut, Lebanon

c GPM-UMR-CNRS 6634, Universite´ de Rouen, BP 12 76801, Saint Etienne du Rouvray Cedex, France