Gate Charge characteristics investigation of Negative Bias Temperature Instabilities in POWER MOSFET Reliability,

                                                   Communication : EMRS 2006, Nice

Gate Charge characteristics investigation of Negative Bias Temperature Instabilities  in POWER MOSFET Reliability

                                     M. Alwan B. Beydoun  K. Ketata and M. Zoaeter

 Abstract:

In spite of continuous scaling down of the dimensions of CMOS devices, widespread utilization of MOS technology for the realization of power devices and ICs has lead to an increased interest in ultra-thick gate oxides as well. The negative bias temperature stress induced instabilities of threshold voltage, Input capacitance, the Miller capacitance and the energy which is the product of the gate charge and the gate voltage required for switching. The Power MOSFET stressed with negative gate voltage under precision Temperature Forcing System in the range –55-175°C (Thermal operating, TCT and TST test). The Gate charge characteristics used for interpreted and analyzed in terms of the mechanisms responsible of parameters degradations and based of the device physical proprieties. The main degradation issue in Si Power MOSFET is the charge trapping and trap creation in the gate dielectric and at the interface by energetic free carriers which have sufficient energy to cross the Si-SiO2 barrier. The carrier heating is achieved by drift in the depletion region adjacent to the interface. The hole trapping, dissociation of the SiH bands by electric field, and various electrochemical reactions involving both oxide and interface defects and water-related species were shown to be the mechanisms responsible for buildup of oxide charge and interface traps.